A new generation of PLA for the C64 is now available.

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janilaa
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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Thu Jun 15, 2017 9:20 am

eslapion wrote:
Sat Jun 10, 2017 8:33 am
Even if J-PLA has the very exact timing of a genuine Commodore PLA, its outputs has a slew rate that's off the charts when compared to the real thing and this makes it a massive noise generator.

Only the 10ns version of the XC9536XL with its slew rate limiter enabled offers signals that are similar in nature to antique NMOS and TTL signals. You look at that on a good scope and you can't see the difference from a vintage 74LS series chip.
That is just not true. I now have a 200MHz scope and have being doing some measurements... some results below.

Image

Image

Here I have measured !CHAROM -signal (all signals are pretty same, doesn't matter which I selected).
These measurements have been made on a real 250466 mainboard using a 150MHz probe with 10x setting on and a very short
spring-type ground contact.

I pasted the images on top of each other, so that it's easier to see differences (which doesn't exist!).
I do find it a bit suprising that your 10ns chip and my 5ns, both genuine, have so similar results, there is hardly any
noticeable differences in slew rates.

As you (and everyone else) can see, there is no ringing on J-PLA either.
Slew rates on both PLAnkton and J-PLA are faster than any original PLA, but I don't find that problem at all.
If that slew rate makes J-PLA a "massive noise generator", then yours is like that too.

I wonder if that 5ns chip you have been measuring had "slow slew rate" and "low power" -modes activated?
And was it a genuine chip? You have been telling that counterfeits don't have working slew rate control, so did you
actually measure a fake chip and now your "facts" are based on that?



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eslapion
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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Fri Jun 16, 2017 1:19 am

I have 2 important questions for you:

1. Did you enable the slew rate limiter (on all 8 outputs) on the unit you sold to e5frog ?
2. Did you take these measurements while the units are attached to an actual C64 board ? (added edit: apparently yes, you specified a 250466)
I wonder if that 5ns chip you have been measuring had "slow slew rate" and "low power" -modes activated?
It's you who built and sold the unit and I didn't try to read back it's programming - I assumed you locked the chip.
... you tell me!

Added edit:
Its a good thing you used the !CHAROM line; the capacitor and resistor on the !CASRAM line would have altered the results.

You have my attention. I will try and capture what I have on the TDS-1002 here. I also have a board 250466 available here but I am more concerned with what happens with old boards 250407 and 326298.

Added edit 2:
On some oscilloscopes, it is possible to activate a bandwidth limiter - my own TDS-1002 has that feature - you didn't happen to use such a feature, did you ? This would mask high frequency ringing.
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

janilaa
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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Fri Jun 16, 2017 8:59 am

eslapion wrote:
Fri Jun 16, 2017 1:19 am
I have 2 important questions for you:

1. Did you enable the slew rate limiter (on all 8 outputs) on the unit you sold to e5frog ?
Sure, I have had slew rate limiter and low power mode enabled on all 8 outputs in every J-PLA I have sold.
I still have some of those early J-PLA's in my own machines and tested those too, every J-PLA had almost identical results as these
current versions using CPLD's from authorized distributor. As said before, those early one's had same delay also on !CASRAM, which I changed to my current 1.10 version, that was the only change in programming.
I wonder if that 5ns chip you have been measuring had "slow slew rate" and "low power" -modes activated?
It's you who built and sold the unit and I didn't try to read back it's programming - I assumed you locked the chip.
... you tell me!
It's locked alright, but I was referring to those 5ns chips that you have tested during PLAnkton development and to which you seem to base your facts about 5ns version being improper alternative for building a PLA substitute.

You said earlier that you had tested PLAnkton on a 5ns chip and did see something that was "obvious to me you should never use the 5ns versions to make a C64 PLA substitute".
Did you have slew rate limiter and low power mode activated on those 5ns chips and were those chips genuine?
Added edit:
Its a good thing you used the !CHAROM line; the capacitor and resistor on the !CASRAM line would have altered the results.
I'm fully aware of capacitor & resistor on 250466 and sometimes disable those, or just use some other board that doesn't have them.
In fact I also measured !CASRAM on both PLAnkton and J-PLA on this board with R&C disabled and the results were similar, no noticeable differences.
You have my attention. I will try and capture what I have on the TDS-1002 here. I also have a board 250466 available here but I am more concerned with what happens with old boards 250407 and 326298.
I've done some measurements on those boards too, not much difference. When measuring those signals from the ROM-chips for example, I see some bumps on signals after edges, which I wouldn't call exactly ringing... and I see those with real Commodore PLA's too.
I also checked quite a bunch of original PLA's and those late 906114-01's seem to have slew rates that are only a bit slower than our products, other original PLA's have slew rates quite a bit slower (especially on rising edges).
Added edit 2:
On some oscilloscopes, it is possible to activate a bandwidth limiter - my own TDS-1002 has that feature - you didn't happen to use such a feature, did you ? This would mask high frequency ringing.
The scope has 20MHz bandwith limiter, which was turned off ofcourse. With a regular ground wire I see ringing and the scope is very sensitive to even moving the probe cables, so I'm pretty sure the scope is capable of measuring high frequency ringing if there is such.

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eslapion
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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Fri Jun 16, 2017 4:48 pm

janilaa wrote:
Fri Jun 16, 2017 8:59 am
It's locked alright, but I was referring to those 5ns chips that you have tested during PLAnkton development and to which you seem to base your facts about 5ns version being improper alternative for building a PLA substitute.

You said earlier that you had tested PLAnkton on a 5ns chip and did see something that was "obvious to me you should never use the 5ns versions to make a C64 PLA substitute".
Did you have slew rate limiter and low power mode activated on those 5ns chips and were those chips genuine?
I have used the 5ns version of the XC9536XL in 2 different contexts.

The first one was a trial on a pre-release version of PLAnkton using the unlocked code of PLAnkton with a version of the delay system that uses one fewer block than the normal version. On all versions of the PLAnkton code, both the low power mode and slew rate limiters are forced active.

The second one is on a PLAnkton module modded to act as a test bench in the course of the development of a new product called GandALF. On this test bench, the PLAnkton module was programmed to emulate the behavior of various 74LS chips that have registered logic in them. In this specific case, the low power mode was always active but different trials were run with the slew rate limiters active and inactive to see the impact on power usage and signal quality.

On both instances it appeared using the more expensive 5ns version degraded signal quality and increased the cost for no good reason.
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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Gyro Gearloose
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Re: A new generation of PLA for the C64 is now available.

Post by Gyro Gearloose » Sat Jun 17, 2017 6:28 pm

Wow, all this is so nostalgic for me, not only for the Commodore aspect. In my first tech job I designed this

Image

It's been 20 years, maybe someone can refresh my memory. I remember running OrCAD on my 386 Bridgeboard at home. Actually it was called OrCAD SDT 386+ at the time. It was better than what Cadence is pushing today IMO. Anyways I was using the OrCAD logic tool called SDT PLD 386+, IIRC. It was based on PALASM I think. They also had a schematic capture but even then I knew this was nonsense.

Ahhh back then, college was teaching a hell of a lot more in electronics than just a few years later. I had just finished a course on the Intel EPLD and I knew what I was doing. I somehow convinced my boss at the time to let me redesign the whole thing, to replace this truly messy arrangement of 74xx chips. They had figured out the logic in some kind of two bit finite state machine which was correct, but all the real-world hardware implementation was abysmal. Bad power supply, no buffering, no consideration of fan out, etc.

I wish I were young again, I know less today than back then!

I couldn't make my own PLA substitute today. Mostly because I lost interest. But it was tremendous fun back then.

I also remember, as a service tech, I had to repair Sonatest portable ultrasonic testers. They were used in the field and usually came back dirty, juicy, cracked, etc. But they were quite expensive, so people insisted we repair 1970s instruments. This is were I got a real world lesson in logic levels and rise-times. You couldn't just pop the then-new 74 logic like F, LS, S, or HC, into a large two-layer PCB designed for 74/54 straight TTL.

Eventually I figured out that slowing down the chips with a resistor on the VCC (10 ohms? 100 ohms? I don't recall.) slowed the output enough so it ringed less and only lost a few mV on the VCC.

This was just before the internet became big, I had no easy way to get datasheets, no easy way to shop for chips, I had to use whatever datasheets the faxback would get me, or the physical databook library, and had to make do with whatever chips we had in stock.

Ordering parts took a few days since I had to fill out a request which went to the stock guy, who'd wait to get a big enough order to go to Electrosonic!

I felt better after Sonatest themselves used the same approach for their repairs. I even was sent to England to meet the crew! They were a great bunch.

Ahhhh nostalgia. Now excuse me, it's time for my afternoon nap.

Please carry on your fights, it is delightful. Almost as much fun as a IBM vs Commodore argument in the schoolyard!
The price one pays for pursuing any profession, or calling, is an intimate knowledge of its ugly side.

janilaa
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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Sun Jun 18, 2017 4:07 pm

I've been doing some measuring again...

My scope can show rise & fall times. Falling times it calculates from signal levels from 90% to10% and rising from 10% to 90%. I let the scope take 50 measurements from each tested chip and calculate a mean value out of those.
I took 10 J-PLA's (with 5ns CPLD's I received last week from Digikey, date code 1713) and selected slowest and fastest among them to be tested. These results are again from !CHAROM -signal.

Here's the results:
PLAnkton: fall time 2.24ns, rise time 3.10ns.
Slowest J-PLA: fall time 2.54ns, rise time 3.42ns
Fastest J-PLA: fall time 2.20ns, rise time 3.42ns
J-PLA with a 10ns chip: fall time 2.56, rise time 3.46ns.

So, from the set of 10 J-PLA's with 5ns CPLD's only the fastest had shorter fall time than PLAnkton.
These results leads me into thinking that Xilinx is currently making only one version of the chip despite the speed grade -markings on top.

I also measured the propagation delays with this scope... on !CASRAM I get about 36ns on plankton, which is about the value you have told, but on those other 7 signals I get about 10.5ns which is quite far from your target.
On J-PLA I get about 28-30ns on !CASRAM and 26-28ns on other signals, which is really close to my target.

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Gyro Gearloose
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Re: A new generation of PLA for the C64 is now available.

Post by Gyro Gearloose » Sun Jun 18, 2017 6:17 pm

I get the feeling the real purpose of making PLA substitutes is to create drama and show off that you have a scope.

Newsflash. Electronics is over and total nooblers have scopes now. No one's impressed your scope can measure rise-times. My 50 year old Tektronix 567 can do that too.

There was literally no other reason to make yet another completely indistinguishable product for a higher price, and then come in and argue.
The price one pays for pursuing any profession, or calling, is an intimate knowledge of its ugly side.

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eslapion
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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Sun Jun 18, 2017 8:05 pm

janilaa wrote:
Sun Jun 18, 2017 4:07 pm
Here's the results:
PLAnkton: fall time 2.24ns, rise time 3.10ns.
Slowest J-PLA: fall time 2.54ns, rise time 3.42ns
Fastest J-PLA: fall time 2.20ns, rise time 3.42ns
J-PLA with a 10ns chip: fall time 2.56, rise time 3.46ns.

So, from the set of 10 J-PLA's with 5ns CPLD's only the fastest had shorter fall time than PLAnkton.
These results leads me into thinking that Xilinx is currently making only one version of the chip despite the speed grade -markings on top.
For different reasons, I tend to come to the same conclusion.

Current XC9536XL rated for 10ns appear to react much faster than those purchased in 2015.
I also measured the propagation delays with this scope... on !CASRAM I get about 36ns on plankton, which is about the value you have told, but on those other 7 signals I get about 10.5ns which is quite far from your target.
On J-PLA I get about 28-30ns on !CASRAM and 26-28ns on other signals, which is really close to my target.
It is my opinion that you have elected to implement a couple of features in J-PLA which don't change much to achieve the desired result which is to have an operational PLA which works well on all C64 boards as well as accommodate for the HC chips installed on the C64 Reloaded.

Having a delayed response on all outputs is one of them. It's 'neat' but truly not necessary.

I assume since these extra delays require more blocks to be actively utilized in the CPLD, if the 5ns and 10ns version are essentially the same product, these extra blocks would explain why J-PLA consumes more power (when not counting the extra 5-6mA required for the voltage regulator).
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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eslapion
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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Wed Jun 21, 2017 12:32 pm

Sizzling summer special!

Get PLAnkton at it's older price for the summer: 14 Euros or 15.50$US per unit
Add one or more TOLB to your order and get 10% discount on that special price, that's 12.60 Euros or 13.95$US per unit!

Shipping remains the same price. This offer expires Sept.20th 2017

Also, customers ordering 10 units or more get a 25% discount. Customers ordering 5 units or more get a 20% discount. TOLB discount does not apply to these quantity discounts.

-----

900 units sold as of June 23rd!
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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Re: A new generation of PLA for the C64 is now available.

Post by Oge_user » Sun Jun 25, 2017 4:19 pm

Gyro Gearloose wrote:
Sun Jun 18, 2017 6:17 pm
I get the feeling the real purpose of making PLA substitutes is to create drama and show off that you have a scope.
I completely agree. PLAnkton just does its job good and costs even less than an used Commodore PLA, which goes for insane price when bought from eBay and - when not bought in New Old Stock condition - cannot be expected to work for long periods of time.

Finding a New Old Stock PLA was something possible some years ago, now it is rare enough that - from my point of view - if you are lucky enough to find one from a ol' man electronic store, then reselling would be an unwise move. I would personally keep the mint PLAs for future preservation and just use a PLAnkton.
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