A new generation of PLA for the C64 is now available.

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janilaa
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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Thu Jun 08, 2017 8:33 pm

eslapion wrote:
Thu Jun 08, 2017 4:33 am
I am rather pissed here...
Why? Have I said something bad about your products? Or have I been badmouthing your electronics skills or knowledge? Or your soldering procedures?
Or maybe I have been spreading around rumors about your product not based on any facts?
I think I'm the one that should be pissed!
eslapion wrote: For one thing, a voltage regulator, to me, is an indicator of lack of knowledge in electronics. It's just extra parts to impress gullible people.
My choice of using a regulator may steal 6 mA of current, but for that I get steady voltage that does not fluctuate with input voltage or current the CPLD is using, like a plain resistor and a diode does. With this 6 mA I also get protection for the CPLD for overvoltage that using original C64 power supply may cause (yes, there are still people using original power supplies!), and a protection for inserting PLA accidently to a SID socket.
And raising voltage with resistor on ground pin isn't a "hack" if that was what you were trying to say earlier... it's perfectly valid method described in regulator's datasheet.
eslapion wrote: For another, this '5ns for accurate' thing is major horse manure - genuine Commodore PLAs themselves have enormous response speed discrepancies; from 24 to 38ns - a 60% variation.
My goal was 25ns based on my measurements on 906114-01. And to achieve that I chose 5ns version over 10ns, because using 5ns "blocks" would get me exactly to my goal (5x5ns -> 25ns) instead
of using 10ns "blocks" that would have got me into either 20ns or 30ns (2x10ns or 3x10ns) delay. After receiving the parts I found out that there is a lot more things involved with
the timing, but nevertheless the same principle stays. Using a faster chip enables you to use shorter "building blocks" and thus getting more accurately to your goal.
eslapion wrote: Third, PLAnkton is correctly delayed on all outputs. CASRAM requires more but otherwise, the low power mode and slew rate limiters do all that's needed.
I agree that it's pretty close to the rearest original PLA - 251064-01.
eslapion wrote: Last but not least, the latest 'incarnation' of J-PLA suddenly have new parts added on the underside. Apparently a result of me posting more technical information here. If emulation is the sincerest form of flattery then I could definitely do without this one...
I had already ordered new PCBs (with pads new parts) ordered when I shipped the J-PLA to e5frog (before any of your comments about J-PLA), I also mentioned that to him (you can check that from him).
The extra parts are added resistor and capacitor like new C64's have (C204 and R42), that can be enabled. Possibly not needed (because of extra delay in #CASRAM inside CPLD) and not enabled by default, but they exists there now incase somebody finds a C64 that needs them.
I did not "emulate" that from you, I put these components after the CPLD output, like the original C64 has after the PLA. Not in middle of two CPLD signals.
eslapion wrote: J-PLA exists because I posted the necessary technical information online on Melon64 nearly 2 years ago. Of course, Mr. Schönfeld and his friends dismissed all that as lunacy coming from Neptune. All Janilaa managed to prove is that he won't so quickly disregard information coming from outside the officially accepted views of the 'Old Boys Club'. He just grabbed information fetched through the hard work of other people and uses it to make his own amateurish replica.
The facts needed to create J-PLA did not come from your or from your posts. The facts needed have been around from the 90's, the exact same information that you used. Your posts don't add any technical information that wasn't available before. Even the CPLD based implementations existed before, you weren't the first one and can't take the credit of that. I did select the same CPLD, that's true, but not for the reason of copying you but only for the reason it seemed like a good alternative. I didn't use any VHLD's found on the net, as using them wouldn't have got me to my goal with the timings. Not even if I would have used 10ns version in low power mode & slow slew rate mode. I made my own VHLD based on the logic equations available on the internet, but made much simplified code (but keeping the logic 100% same) with the stuff needed for the extra delay.

eslapion wrote: Even the solders are inconsistent because they are made one at a time with an ordinary soldering iron using normal soldering procedures. No wave or drag soldering with professional methods and products.
You really should stop guessing things as your bad at it! I would appreciate you asking me if you don't know something, before making guesses and representing these guesses as facts!
I'm using solder paste and hot air rework-station. I'm not using a stencil, so I get occasionally solder bridges between legs, which I the fix with a regular soldering iron. That's how the spike may have formed. I really didn't realise that this was a beauty competition? I thought that it would be enough that all the legs are soldered firmly to the pads...
eslapion wrote: Counterfeit IC rated for 5ns.
I assume you have some REAL evidence for that argument?
eslapion wrote: Manufacture date is 1309 - this chip is 4 years old!!
You may have just found out the reason they were cheaper!
Old stocks might have been sold to a smaller dealer for discounted price.
eslapion wrote: Typeface is smaller and very difficult to read; this photo had to be taken with more lighting and longer exposure.
Check out the following picture...
On the left is a genuine 5ns XC9536XL bought from Digikey and on the right is a 10ns version also bought from Digikey.
The one on left been soldered and after that cleaned with IPA. Cleaning makes the text much harder to read as you see.
Both were originally exactly the same. I don't have any unsoldered 5ns CPLD's right now, but I can assure that they looked exactly same.
Don't get excited about the 10ns version on J-PLA PCB, I'm not still going to use those but I did order some to make some tests.

Image

Also notice the difference in typeface and the logo when compared to your 10ns chip.
My genuine CPLD's have a lot thicker letter I's on the logo. Also the logo is different size, on my sample the registered trademark symbol is
at the second pin from the right in upper row and in yours it's on the third pin. Also the R-symbol is different size.
Our genuine 10ns chips bought from the same distributor have that much differences with
only 4 weeks difference in manufacturing date, imagine how much differences there can be in 4 years.
Even if the CPLD's I can prove to be genuine are that much different from yours, I ain't claiming your
chips counterfeits as I know that there are different plants in different countries manufacturing the same
GENUINE chips and some variation in markings can exist.

And once again for the audience, only few of the first CPLD's on J-PLA were bought from China (which doesn't automatically mean they are counterfeits).
I can't prove them to be genuine (and neither can eslapion prove them not to be genuine), but they have exactly same electrical characteristics and
functionality as the originals and that's why I believe them to be genuine. If any of the those first CPLDs would happen to fail, I'm more than happy to replace those to a J-PLA's with CPLD's I know to be genuine.

The one seen on the left above is the one I'm using currently and have been using for some time already and will use
these in all J-PLA's in the future. I guarantee these to be genuine and purchased from Digikey, which is large authorized distributor for Xilinx.



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eslapion
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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Thu Jun 08, 2017 9:55 pm

janilaa wrote:
Thu Jun 08, 2017 8:33 pm
Why? Have I said something bad about your products? Or have I been badmouthing your electronics skills or knowledge? Or your soldering procedures?
Or maybe I have been spreading around rumors about your product not based on any facts?
Your advertisement on eBay insinuates that PLAnkton has the proper delay only on the CASRAM output line. It's false.

Your logic analyzer can only verify timing in increments of 5ns. Since PLAnkton responds in 14ns on outputs other than CASRAM, which is smaller than 15ns, your instrument indicates 10ns.
My choice of using a regulator may steal 6 mA of current, but for that I get steady voltage that does not fluctuate with input voltage or current the CPLD is using, like a plain resistor and a diode does. With this 6 mA I also get protection for the CPLD for overvoltage that using original C64 power supply may cause (yes, there are still people using original power supplies!), and a protection for inserting PLA accidently to a SID socket.
And raising voltage with resistor on ground pin isn't a "hack" if that was what you were trying to say earlier... it's perfectly valid method described in regulator's datasheet.
I'm sure everyone insert's their PLA in the SID socket... don't think so!

Using a resistor on the ground line is not a hack. Having a piece of mica inserted under the pin of the regulator is.
My goal was 25ns based on my measurements on 906114-01. And to achieve that I chose 5ns version over 10ns, because using 5ns "blocks" would get me exactly to my goal (5x5ns -> 25ns) instead
of using 10ns "blocks" that would have got me into either 20ns or 30ns (2x10ns or 3x10ns) delay. After receiving the parts I found out that there is a lot more things involved with
the timing, but nevertheless the same principle stays. Using a faster chip enables you to use shorter "building blocks" and thus getting more accurately to your goal.
There you are completely wrong. The 10ns version of the XC9536XL is guaranteed to offer a latency of less than 10ns upon changes to the entry of a combinatorial logic gate if it is used in normal mode. The actual response speed is between 7.5ns and 8.2ns - I don't have the tools to measure that as it is indicated in the datasheet for the IC, it is the sum of the combinatorial logic propagation delay, the output buffer delay and the input buffer delay.

On the 10ns version of the IC, it represents a variation of about 10%. This sum on the 5ns version is close to 4ns but on this version of the chip, the variation is closer to 25%. The 5ns version of the chip was really designed to use registered logic at speeds close to 150MHz and the slew rate limiter operates differently on that version of the chip.

Only the 10ns version can add up to 10ns of latency on an output transition CONSISTENTLY without the need for registered logic or more gates by using the low power mode which makes the chip leaner and using the slew rate limiter which prevents ringing. THAT is why J-PLA uses more power, NOT because of the regulator.

If your strategy is to cascade 5 logic blocks to achieve a specific delay then these blocks can each vary by 25% on their individual latency. Your logic analyser which runs at only 200MS/s may not show this.

... but in truth IT DOESN'T MATTER AT ALL. As I said earlier, MOS or Commodore PLAs themselves vary in response speed by as much as 60%

Using 5ns chips to be "more accurate" is pure waste. Claiming you use a fast 5ns version of the CPLD for more accurate response speed makes no sense.
Check out the following picture...
On the left is a genuine 5ns XC9536XL bought from Digikey and on the right is a 10ns version also bought from Digikey.
The one on left been soldered and after that cleaned with IPA. Cleaning makes the text much harder to read as you see.
I know both ICs are genuine because of the typeface used, not because the cleaning agent has or hasn't done it's job.

Fake ICs have a smaller typeface and logo. The TM symbol is also not the right position.
Last edited by eslapion on Thu Jun 08, 2017 10:23 pm, edited 1 time in total.
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janilaa
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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Thu Jun 08, 2017 10:17 pm

eslapion wrote:
Thu Jun 08, 2017 9:55 pm
Your advertisement on eBay insinuates that PLAnkton has the proper delay only on the CASRAM output line.

No it does not. It doesn't say anything about PLAnkton.
There are many more alternatives around and I'm sure you can agree that not all of them have correct delays?
I'm sure everyone insert's their PLA in the SID socket... don't think so!
Not everyone, but I've heard it happen. As the chip locations vary between mainboards this is very much possible.
I wasn't thinking that when designing J-PLA, that just came to my mind as one positive feature.
Using a resistor on the ground line is not a hack. Having a piece of mica inserted under the pin of the regulator is.
Ok. That was one of the reasons of making new PCBs, it's already fixed.

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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Thu Jun 08, 2017 10:27 pm

janilaa wrote:
Thu Jun 08, 2017 10:17 pm
There are many more alternatives around and I'm sure you can agree that not all of them have correct delays?
True.
Not everyone, but I've heard it happen. As the chip locations vary between mainboards this is very much possible.
I wasn't thinking that when designing J-PLA, that just came to my mind as one positive feature.
My friend Mitch did it once. The PLAnkton survived - you can probably find the post on Amibay.
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Thu Jun 08, 2017 11:12 pm

eslapion wrote:
Thu Jun 08, 2017 9:55 pm
There you are completely wrong. The 10ns version of the XC9536XL is guaranteed to offer a latency of less than 10ns upon changes to the entry of a combinatorial logic gate if it is used in normal mode. The actual response speed is between 7.5ns and 8.2ns - I don't have the tools to measure that as it is indicated in the datasheet for the IC, it is the sum of the combinatorial logic propagation delay, the output buffer delay and the input buffer delay.

On the 10ns version of the IC, it represents a variation of about 10%. This sum on the 5ns version is close to 4ns but on this version of the chip, the variation is closer to 25%. The 5ns version of the chip was really designed to use registered logic at speeds close to 150MHz and the slew rate limiter operates differently on that version of the chip.
The datasheets I'm reading say that that the propagation delay is sum of T_IN(input buffer), T_LOGI(internal logic), T_PDI(Combinatorial logic) and T_OUT(output buffer).
For 10ns version datasheet also defines the maximum delays:
T_IN 3.5ns
T_LOGI 1.8ns
T_PDI 1.7ns
T_OUT 3.0ns

That makes a total of 10ns like the chip's indicated speed. Your calculation seems to be missing the internal logic delay?
I find only the maximum delays on datasheets. Where have you found out the variation of 10% ?

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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Fri Jun 09, 2017 10:43 pm

eslapion wrote:
Thu Jun 08, 2017 9:55 pm
Only the 10ns version can add up to 10ns of latency on an output transition CONSISTENTLY without the need for registered logic or more gates by using the low power mode which makes the chip leaner and using the slew rate limiter which prevents ringing. THAT is why J-PLA uses more power, NOT because of the regulator.
Wrong! Regulator uses additional 5,7mA, I have just measured it.
I also measured both J-PLA's and PLAnktons current consumption when fed from the same 3.60v source on a real working C64.
J-PLA uses 25,6mA and PLAnkton 21,9mA. Thats a only of 3,7mA more current on my CPLD logic!
Both replacement PLA's had the voltage drop components removed for the tests.

When both installed on C64 just like they are, PLAnkton with the resistor and diode, J-PLA with regulator the results are:
J-PLA 31,3mA and PLAnkton 23,3mA. So total difference is only 8mA, which is totally insignificant if compared to the original PLA's which can use over three times more current than J-PLA.

On my sample of PLAnkton the measured voltage on CPLD is 3,67v which is over the Xilinx's recommended max voltage.
This overvoltage also makes the PLAnkton use more current, as when fed with exactly 3,60v the current was 21,9mA.
The 5v rail on my test-board had 4,91v. If it would have been 5,24v, PLAnkton would have hit CPLD's Absolute Maximum Rating.

Using regulator keeps voltage exactly on the designed level and gives much cleaner output.
The insignificant amount of extra current and the very low additional cost of regulator is no excuse of not using a regulator.

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Re: A new generation of PLA for the C64 is now available.

Post by Gyro Gearloose » Sat Jun 10, 2017 1:50 am

I am quite happy with my PLAnktons.
The price one pays for pursuing any profession, or calling, is an intimate knowledge of its ugly side.

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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Sat Jun 10, 2017 4:08 am

janilaa wrote:
Fri Jun 09, 2017 10:43 pm
I also measured both J-PLA's and PLAnktons current consumption when fed from the same 3.60v source on a real working C64.
J-PLA uses 25,6mA and PLAnkton 21,9mA. Thats a only of 3,7mA more current on my CPLD logic!
Both replacement PLA's had the voltage drop components removed for the tests.

When both installed on C64 just like they are, PLAnkton with the resistor and diode, J-PLA with regulator the results are:
J-PLA 31,3mA and PLAnkton 23,3mA. So total difference is only 8mA, which is totally insignificant if compared to the original PLA's which can use over three times more current than J-PLA.

On my sample of PLAnkton the measured voltage on CPLD is 3,67v which is over the Xilinx's recommended max voltage.
This overvoltage also makes the PLAnkton use more current, as when fed with exactly 3,60v the current was 21,9mA.
The 5v rail on my test-board had 4,91v. If it would have been 5,24v, PLAnkton would have hit CPLD's Absolute Maximum Rating.

Using regulator keeps voltage exactly on the designed level and gives much cleaner output.
The insignificant amount of extra current and the very low additional cost of regulator is no excuse of not using a regulator.
I did tests with PLAnkton at 5.3V (even higher than the 5.24V you mention - on a test bench, not inside a C64) and Vcc at the CPLD did not reach 4.0V because the current consumed by the CPLD increases (as you have mentioned yourself) and the voltage drop across the resistor increased. Anyways, at 5.24V on the 5V rail in a C64, the DRAM chips begin to suffer permanent damage.

Xilinx's recommended maximum operating voltage for the XC9536XL is 3.6V but the absolute maximum Vcc is 4.0V and PLAnkton operates well below that. There is a couple of reasons for using a higher voltage but one stands out in particular.

NMOS and TTL logic components have a logic threshold voltage of close to 1.3V. Given a specific slew rate on signal voltage variation, it will take more time to reach that threshold voltage when activating an output (going from high to low) than it does when deactivating an output (going from low to high). This time imbalance is made even greater when using the slew rate limiter which has the greatest impact on the 10ns version of the chip.

The consequence is that when doing a transition from signaling active one output to another, there will be a brief period of time during which all outputs are above 1.3V and therefore none of the 8 are considered active - a sort of dead time which prevents bus contentions. The higher Vcc is, the greater this period of time is.

1. Very often, people will replace the kernal in their Commodore 64 with newer chips that are more than 5 times faster than the original 2364 ROM chip (JiffyDOS is a good example) so having a dead time on transitions is very important
2. Even with this overvoltage, by your own numbers, PLAnkton uses less power than J-PLA WITHOUT the regulator

I have a 60MHz TDS-1002 and I see absolutely no difference in "cleanlyness" (whatever that is) on the output of the XC9536XL whether it is powered at 3.2V or 3.8V with the slew rate limiter activated. Not using it, however, causes ringing because the C64's traces were not designed to handle high frequency/harmonics signals and they have a lot of parasitic inductance. In the case of the SuperPLA V3 (the MACH210 doesn't have that feature), this ringing causes brief spurious logic value changes (I called them stutters) that I was able to see on the logic analyzer at 500MS/s.

Just FYI, I also ran tests on the prototypes of PLAnkton having the CPLD powered at 4.3V (one diode and no resistor acting as regulator) and it ran well but I did eventually destroy the CPLD after a few hours of operation like that.
Where have you found out the variation of 10% ?
With my own TDS-1002.

I did make a prototype of PLAnkton that was programmed with the same code but using a 5ns version of the XC9536XL. Since I examined the results with both a 10ns and a 5ns versions of the CPLD and using both a logic analyzer and an oscilloscope, it was obvious to me you should never use the 5ns versions to make a C64 PLA substitute.
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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Re: A new generation of PLA for the C64 is now available.

Post by janilaa » Sat Jun 10, 2017 7:19 am

eslapion wrote:
Sat Jun 10, 2017 4:08 am
Anyways, at 5.24V on the 5V rail in a C64, the DRAM chips begin to suffer permanent damage.
4164 DRAM chips have recommended max input voltage of 5.5v, which you should not exceed.
Just like you should not exceed Xilinx's 3.6v, because sometimes permanent damage can happen even
below the recommended max voltages.
eslapion wrote: NMOS and TTL logic components have a logic threshold voltage of close to 1.3V. Given a specific slew rate on signal voltage variation, it will take more time to reach that threshold voltage when activating an output (going from high to low) than it does when deactivating an output (going from low to high). This time imbalance is made even greater when using the slew rate limiter which has the greatest impact on the 10ns version of the chip.

The consequence is that when doing a transition from signaling active one output to another, there will be a brief period of time during which all outputs are above 1.3V and therefore none of the 8 are considered active - a sort of dead time which prevents bus contentions. The higher Vcc is, the greater this period of time is.
In J-PLA this dead time is done in logic programming, without need to go over the recommended voltage.
eslapion wrote: 2. Even with this overvoltage, by your own numbers, PLAnkton uses less power than J-PLA WITHOUT the regulator
J-PLA's timing is based on the most popular PLA found on C64's. To achieve that, a very small addition (3,7mA) of current
was required.

Original PLA's use current between about 25mA and 105mA. 105mA is used by the original 82S100.
The very rare PLA (251064-01) you have used as a reference for your design uses only about 25mA of current.
PLAnkton is therefore using only about 6% less current than a real original PLA (not 1/5th as advertised).

The scale of original PLA's current consumption being between 25mA and 105mA, both J-PLA and PLAnkton
are doing great there (Plankton with 23,3mA and J-PLA with 31,3mA).

And in real life that small difference in current consumption doesn't mean anything.
eslapion wrote:
Where have you found out the variation of 10% ?
With my own TDS-1002.
And just 2 days before you were claiming that you don't tools to measure that (quote below) and
were referring to a datasheet which I proved to have no such information.
eslapion wrote:
Thu Jun 08, 2017 9:55 pm
There you are completely wrong. The 10ns version of the XC9536XL is guaranteed to offer a latency of less than 10ns upon changes to the entry of a combinatorial logic gate if it is used in normal mode. The actual response speed is between 7.5ns and 8.2ns - I don't have the tools to measure that as it is indicated in the datasheet for the IC, it is the sum of the combinatorial logic propagation delay, the output buffer delay and the input buffer delay.

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Re: A new generation of PLA for the C64 is now available.

Post by eslapion » Sat Jun 10, 2017 8:33 am

janilaa wrote:
Sat Jun 10, 2017 7:19 am
In J-PLA this dead time is done in logic programming, without need to go over the recommended voltage.
Well, in both PLAnkton and all genuine Commodore PLAs, this dead time is a virtue of a slow transition on the outputs.
J-PLA's timing is based on the most popular PLA found on C64's. To achieve that, a very small addition (3,7mA) of current
was required.

Original PLA's use current between about 25mA and 105mA. 105mA is used by the original 82S100.
The very rare PLA (251064-01) you have used as a reference for your design uses only about 25mA of current.
PLAnkton is therefore using only about 6% less current than a real original PLA (not 1/5th as advertised).

The scale of original PLA's current consumption being between 25mA and 105mA, both J-PLA and PLAnkton
are doing great there (Plankton with 23,3mA and J-PLA with 31,3mA).

And in real life that small difference in current consumption doesn't mean anything.
About 2 years ago, Jens Schönfeld said I think too much in analog terms well, it seems to me you think too much in pure digital terms.

What makes the Commdore PLA well adapted to the rest of the computer and especially the traces on its circuit boards is the low slew rate (by today's standards) of its signals.

Even if J-PLA has the very exact timing of a genuine Commodore PLA, its outputs has a slew rate that's off the charts when compared to the real thing and this makes it a massive noise generator.

Only the 10ns version of the XC9536XL with its slew rate limiter enabled offers signals that are similar in nature to antique NMOS and TTL signals. You look at that on a good scope and you can't see the difference from a vintage 74LS series chip.

You boast J-PLA has the same response speed as "the most popular" genuine PLAs, well PLAnkton consumes 1/5 the power of "the most popular" genuine PLAs and it certainly does consume 1/3 the power of the SuperPLA V3. As if PLAs were popular - people didn't get to choose them. Some models were more prevalent.

I didn't even know the 251064-01 only consumes 25mA, which I find very surprising, but if it does then I guess I really did reproduce it in virtually every aspect.
eslapion wrote:
Where have you found out the variation of 10% ?
With my own TDS-1002.
And just 2 days before you were claiming that you don't tools to measure that (quote below) and
were referring to a datasheet which I proved to have no such information.
You have a very hard time to reconcile apparent contradictions.

I couldn't possibly measure the response speed of one specific block so I did exactly like you, I cascaded a bunch. If you look at PLAnkton, it has at least 3 external pair of IOs joined together (the last one has an RC filter inserted in between but it can be deactivated), this is a cascade of blocks used to generate the delay system of !CASRAM.

Every time I sell a PLAnkton, I check this delay to make sure it's okay so I can see the range of variations over the hundreds of units I have sold. Of course, it is only of interest here when the RC filter is bypassed.
Just like you should not exceed Xilinx's 3.6v, because sometimes permanent damage can happen even
below the recommended max voltages.
Oh! Please... I've been using my own PLAnktons here with a PSU providing enough to have the Vcc inside my own board 250466 at 5.1V and this results in the CPLD getting 3.72v. I've been running this way since july 2015, before the official release and used this setup for thousands of hours since with no problem and absolutely no degradation of performance.

I am quite sure they could perform like this indefinitely with 3.8v.

Added edit:
BTW, if the XC9536XL consumes more power when Vcc is higher, it's not because it causes any real problem to have it's Vcc higher than 3.6v but because C64 traces have a rather high parasitic capacitance. The energy stored is calculated as 0.5xCxV^2 (in joules) so every time the logic value on these lines is shifted, that much energy is simply lost and as you can see, this amount of energy increases to the square of the voltage. These logic values shift occur about 2 million times every second.
Wealth, like happiness, is never attained directly. It comes as a by-product of providing a useful service. -Harland D. Sanders

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