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-- The REU is actually really simple.
-- There are 4 modes of operation, and 4 active states:
-- r = reu read, w = reu write, R = c64 read, W = c64 write
-- Copy from c64 to reu (00): Rw
-- Copy from reu to c64 (01): rW
-- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW)
-- Verify (11): rR (Rr or rR)
-- The smallest implementation is very likely when only one bit is needed to sel
ect between
-- transition options, and reducing the total number of transitions makes sense
too.
I'm guessing the memory handling (refreshes, etc.) can be handled by off the shelf VHDL routines, dropped into the project.
In fact these days, the 100 ns access time of the RAM in the original REU's is easily achieved by Flash memory. A new design REU with Flash storage or a jumper to choose between cheap DRAM and Flash modules (different sockets) would make the project more worthwhile and attractive. Again, I'm betting the VHDL to drive all this is already out there for the taking. It just needs to be put together into an inexpensive, low end FPGA and built.