What the %$@# is up with links from certain other forums?

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eslapion
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Re: What the %$@# is up with links from certain other forums?

Post by eslapion » Wed Mar 08, 2017 2:17 pm



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Re: What the %$@# is up with links from certain other forums?

Post by Gyro Gearloose » Thu Mar 09, 2017 2:36 am

Wow, Marvin Heemeyer could have done wonders with that!
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Re: What the %$@# is up with links from certain other forums?

Post by JimDrew » Thu Mar 09, 2017 11:05 pm

FYI: TTL logic ICs AND Commodore 65XX/85XX MOS/CSG ICs have a logic threshold of 1.3V while 5V powered CMOS HC chips have a logic threshold of 2.5V. Using HC chips as direct substitutes for TTL-LS chips is WRONG. You MUST use HCT chips if you want to move from TTL to CMOS.
This is where you are confused. When a device provides either 0 or 5 volts (aka logic low or logic high), it's doesn't matter what the actual signal voltage is as long as you can meet the min/max requirements. There is no danger of a latch-up or adverse condition because you are absolutely 100% guaranteed (with the Supercard+ board) to not have any situation where there is an incorrect logic level. As long as you can meet the maximum logic low and minimum logic high voltages, you can certainly interface any type of chips together. However, there is a fan out difference between family of chips that needs to be taken into consideration.

What "logic" threshold are you are referring to above anyways? The center swing voltage differential? That only affects the propagation delay, not the trigger thresholds. If you are referring to the trigger threshold (VIL/VIH), then the HC and HCT parts are not what you are quoting. See for yourself:

http://media.digikey.com/pdf/Data%20She ... 010_ds.pdf
http://media.digikey.com/pdf/Data%20She ... HCT138.pdf

VOL and VOH are identical for the HC and HCT. If you go by the 4.5v table, VIL for the HC part is 1.35v and .8v for the HCT part. This means that a logic low (0) is anything under 1.35v with either chip, but the HCT requires an even lower "low". VIH is for the HC part is 3.15v and 2.0v for the HCT part. This means that HC part requires a higher "high" than the HCT part. The 6502 drives the bus to near 0v (.3v max low level, according to a scope) for a low and near 5v (4.91v on a drive I just tested) for a high. Clearly, these levels are well within the specifications for the HC, or any other 74xx series family for that matter. The HC parts are slightly faster, so even with the center swing differential voltage, the propagation delays are basically the same compared to the HCT version.

Supercard+ for the 1541 (non-1571 version) uses LS chips. LS chips do not work in the 1571 version because the long cable makes the bus noisy. Switching to the HC/HCT (we shipped boards with both types) fixed the bus noise problem. Both types of chips worked, and have worked for the last 28 years. Right now I am shipping Supercard+ boards with 74ACT138 chips:

http://www.onsemi.com/pub_link/Collater ... C138-D.PDF

A little faster and lower power, but the VIL and VIH are 1.5/1.5 typical. You have to remember that in a 5v TTL system, you really are expecting either 0 or 5v. You are never suppose to have anything floating unless it's designed to be Z stated deliberately to eliminate bus contention (like when a device such as an EPROM is not enabled).

There is an excellent tutorial on the differences between CMOS and TTL, and the interface requirements:

https://www.allaboutcircuits.com/textbo ... ge-levels/

You will see here that as long as logic high/low is guaranteed (which I can in my application), there are no issues interfacing TTL to CMOS (and vice-versa).

Certainly, if you designed a device where VIL/VIH fluctuated into realm of incompatibility between TTL/CMOS levels (or insufficient drive, which is a big issue) you could have a problem with your design. In the case of Supercard+ there is no possibility of this occurring. So, I hope that this information clears up any misconceptions one might have about HC and HCT chip usage in my product.

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Re: What the %$@# is up with links from certain other forums?

Post by eslapion » Fri Mar 10, 2017 4:56 pm

JimDrew wrote:
Thu Mar 09, 2017 11:05 pm
This is where you are confused. When a device provides either 0 or 5 volts (aka logic low or logic high), it's doesn't matter what the actual signal voltage is as long as you can meet the min/max requirements. There is no danger of a latch-up or adverse condition because you are absolutely 100% guaranteed (with the Supercard+ board) to not have any situation where there is an incorrect logic level. As long as you can meet the maximum logic low and minimum logic high voltages, you can certainly interface any type of chips together. However, there is a fan out difference between family of chips that needs to be taken into consideration.
I'm not confused at all. Everything you say above is true but there are critical details you fail to take into consideration.
What "logic" threshold are you are referring to above anyways? The center swing voltage differential? That only affects the propagation delay, not the trigger thresholds. If you are referring to the trigger threshold (VIL/VIH), then the HC and HCT parts are not what you are quoting. See for yourself:

http://media.digikey.com/pdf/Data%20She ... 010_ds.pdf
http://media.digikey.com/pdf/Data%20She ... HCT138.pdf
I am referring to the trigger threshold and the numbers you see there are "worst case scenario". In the real world, if you use an ordinary 74HC(T)04 fed with a triangle wave to check at EXACTLY which voltage the input is considered high or low and your components are powered with exactly 5Vdc (NOT 4.5V) then you'll see virtually all manufacturers switch from low to high or high to low at 1.3V for HCT and at 2.5V for HC. 74HC series of chips can operate with a Vcc from 2 to 6 Vdc and the threshold between low and high is generally considered 50% of Vcc.
VOL and VOH are identical for the HC and HCT. If you go by the 4.5v table, VIL for the HC part is 1.35v and .8v for the HCT part. This means that a logic low (0) is anything under 1.35v with either chip, but the HCT requires an even lower "low". VIH is for the HC part is 3.15v and 2.0v for the HCT part. This means that HC part requires a higher "high" than the HCT part. The 6502 drives the bus to near 0v (.3v max low level, according to a scope) for a low and near 5v (4.91v on a drive I just tested) for a high. Clearly, these levels are well within the specifications for the HC, or any other 74xx series family for that matter. The HC parts are slightly faster, so even with the center swing differential voltage, the propagation delays are basically the same compared to the HCT version.

Supercard+ for the 1541 (non-1571 version) uses LS chips. LS chips do not work in the 1571 version because the long cable makes the bus noisy. Switching to the HC/HCT (we shipped boards with both types) fixed the bus noise problem. Both types of chips worked, and have worked for the last 28 years. Right now I am shipping Supercard+ boards with 74ACT138 chips:

http://www.onsemi.com/pub_link/Collater ... C138-D.PDF
This fails to take into account 3 very important details:

- 74LS series chips are designed to be powered +/-5% of 5Vdc BUT they can signal a logic low (0) as high as 0.7V and they may signal a logic high (1) as low as 2.4V which is much lower than the 3.15V you mentioned above - THAT's where the compatibility problem with HC chips lies.

- The MOS 6502 which uses NMOS technology will signal at the voltages you mentioned IF and only IF it has almost no impedance load. In reality it drives a logic low (0) with a few milliamps so it can accommodate for the impedance load of a few 74LS chips - these chips' input impedance are equivalent to a 20kOhms pull-up resistor. However, NMOS ICs (all of them, not just the 6502) drives a logic high (1) with only a few microamps because it expects to be attached to a load which acts as a pull-up. 74LS chips are actually much less sensitive to noise than all CMOS logic ICs because of the type of impedance they present. You are very lucky that both the 1541 and 1571 have only a few ICs attached to their internal databus.

- The cable on your Supercard+ is a very serious problem because it's not shielded and all lines acts as a low value resistors (on the ground and +5V lines too...) and you happen not to have used any decoupling capacitors (or secondary ground line) on the board so if you use 74LS chips on the Supercard+ in a 1571 they draw too much power and the resistive power feed gets a nice generous ground bounce. The ground at the card end of the cable is NOT 0 volts anymore and the +5Vdc is around 4.7V so everything goes haywire... lucky you, an MOS 6502 will work well with only 4.5V and so will 74HC(T) logic ICs

So the bottom line is, the reason why CMOS chips are required on the Supercard+ in a 1571 is not at all the reason you mentioned (bus noise). In reality, HC(T) chips having a much higher input impedance, they are much more sensitive to bus noise. The real reason is that CMOS chips use a lot less power (so they will cause less voltage drop on the cable's Vcc and ground lines) and can operate on a much broader range of Vcc (2 to 6 Vdc for HC and 4.5 to 5.5V for HCT) and are therefore much less sensitive to POWER noise.
A little faster and lower power, but the VIL and VIH are 1.5/1.5 typical. You have to remember that in a 5v TTL system, you really are expecting either 0 or 5v. You are never suppose to have anything floating unless it's designed to be Z stated deliberately to eliminate bus contention (like when a device such as an EPROM is not enabled).
Ignorance at work again.
You will see here that as long as logic high/low is guaranteed (which I can in my application), there are no issues interfacing TTL to CMOS (and vice-versa).

Certainly, if you designed a device where VIL/VIH fluctuated into realm of incompatibility between TTL/CMOS levels (or insufficient drive, which is a big issue) you could have a problem with your design. In the case of Supercard+ there is no possibility of this occurring. So, I hope that this information clears up any misconceptions one might have about HC and HCT chip usage in my product.
Nowhere did you ever take into account that all this is flawed because you have a ground bounce or Vcc instability which is exactly what happens with your Supercard+ in a 1571... because you don't think in terms of electrical architecture like a real engineer does.

This card works because you are lucky...
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Re: What the %$@# is up with links from certain other forums?

Post by ckoba » Sat Mar 11, 2017 1:05 am

Well, to be absolutely fair, the Supercard is neither his idea nor his design. He may well secretly agree with you, but his ego (and his "borrowed" design") won't let him back down.

I did a bit of digging. In the 26 February 1986 issue of Ahoy! (and that date was chosen at random), there are two multi-page advertisments for Megasoft wares (pages 16-17 and 20-21). The first pair hawks "The Keymaster" (a parameter copier that couldn't copy itself) and the infamous Shadow. The second pair is the more standard Megasoft block-ad affair. The "Track Trap" is on the second page, right beneath the "Copy (de)Protection Manual (third edition)". Note that another copy utility on the same page has "by Jim Drew" under the title, so it is likely safe to assume that "Track Trap" was not written by him, but by others. I'll get to that in a minute.

I saw a copy of the "Track Trap" once. It was a pamphlet of instructions on how to add RAM to your 1541 to duplicate raw tracks. Not written nor designed by Jim Drew, but rather a company in Portland called PSIDAC and comprised of two people: Vic Numbers and David Thom. The same guys that wrote the (de)protection manual, actually. The PDF for the manual is on bombjack; I've not been able to find a copy online of "Track Trap", and suspect it may be rather rare. It would be interesting to see what logic family was used there, and thence if Jim just copied that too.

So there's circumstantial evidence that people were expanding the 1541's RAM to go the whole-track route *while* Megasoft was still doing "The Shadow" thing and long prior to Jim's "SuperCard" invention.

Jim wasn't first, nor best. There's a wonderful copyright notice from Bryce Nesbitt out there, allowing most of the known universe the freedom to use snippets of code he posted -- except Jim Drew, who he believed was a prolific thief. Commodore agreed in threads still available via Google groups (and you'll notice that Jim does not deny the allegations above).

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Re: What the %$@# is up with links from certain other forums?

Post by ckoba » Sat Mar 11, 2017 1:21 am

If anyone is curious about the allegations of stolen Commodore code (from David Haynie, no less): https://groups.google.com/d/msg/comp.sy ... EpEwkYsikJ

There was a lot of vitriol towards Jim's cavalier attitude towards consensus reality in the Amiga USENET groups back then. Care to address any of them now, Jim? 'Cause you certainly didn't back then.

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Re: What the %$@# is up with links from certain other forums?

Post by eslapion » Sat Mar 11, 2017 5:04 am

ckoba wrote:
Sat Mar 11, 2017 1:05 am
Well, to be absolutely fair, the Supercard is neither his idea nor his design. He may well secretly agree with you, but his ego (and his "borrowed" design") won't let him back down.
Haa... so that's why he didn't even realize the Supercard+ uses a fake address generator to avoid bus conflicts.

That's probably also why it carries an 8kBytes EPROM but only the first 2k are visible to the CPU even though it contains more than 2k of data!!!
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Re: What the %$@# is up with links from certain other forums?

Post by eslapion » Sat Mar 11, 2017 5:39 am

Sidenote:
A piece of text is missing from my previous post:
A little faster and lower power, but the VIL and VIH are 1.5/1.5 typical. You have to remember that in a 5v TTL system, you really are expecting either 0 or 5v. You are never suppose to have anything floating unless it's designed to be Z stated deliberately to eliminate bus contention (like when a device such as an EPROM is not enabled).
Ignorance at work again. In a 5V TTL system, you are NOT expecting either a 0 or 5V - A logic low (0) is below 0.7V and a logic high is above 2.4V.

Since, as you said yourself, HC chips require 3.15V to determine a logic high, you just DON'T EVER feed TTL signals to an HC chips powered at 5V. Unless, of course, you have no clue what you do.
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Re: What the %$@# is up with links from certain other forums?

Post by ckoba » Sat Mar 11, 2017 6:01 am

eslapion wrote:
Sat Mar 11, 2017 5:39 am
Sidenote:
A piece of text is missing from my previous post:
A little faster and lower power, but the VIL and VIH are 1.5/1.5 typical. You have to remember that in a 5v TTL system, you really are expecting either 0 or 5v. You are never suppose to have anything floating unless it's designed to be Z stated deliberately to eliminate bus contention (like when a device such as an EPROM is not enabled).
Ignorance at work again. In a 5V TTL system, you are NOT expecting either a 0 or 5V - A logic low (0) is below 0.7V and a logic high is above 2.4V.

Since, as you said yourself, HC chips require 3.15V to determine a logic high, you just DON'T EVER feed TTL signals to an HC chips powered at 5V. Unless, of course, you have no clue what you do.
Yeah, that bit is classic Jim. CMOS emits rail-to-rail logic; TTL emits whatever the hell it feels like unless it's an open-collector output or otherwise has pullup/down scheme. And both expect their inputs to be within logic family parameters, which as we keep telling Jim (in vain), differ between classic TTL and HC.

I found quite a few howlers while trawling through Google Groups looking for Jim's greatest misses. Is anyone interested in a post containing a number of links to Jim being caught lying/stealing/cheating?

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Re: What the %$@# is up with links from certain other forums?

Post by eslapion » Sat Mar 11, 2017 10:23 am

ckoba wrote:
Sat Mar 11, 2017 6:01 am
I found quite a few howlers while trawling through Google Groups looking for Jim's greatest misses. Is anyone interested in a post containing a number of links to Jim being caught lying/stealing/cheating?
It might be interesting but I think it's funnier to see him wrap himself in his own technical nonsense.

It never occurred to him the source of the problem with the Supercard+ in a 1571 is the cable doesn't just collect noise, it acts as a resistor skewing the ground and 5V source. The complete absence of small capacitors on the board, especially with that length of cable is a total obvious WTF mistake. :shock:
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