IIRC Addison's sold C16 keyboard mechanisms back in the day when they weren't a Dollarama.
What category does a 'store' fit in when they sell 30 y.o. electromechanical parts in worn out beer bottle crates ?
There are many nice software which will work only on a Plus/4 or C16 with expansion nowadays. I was browsing through Psytronik's stuff yesterday.
Look at this guy which is available for free... https://psytronik.itch.io/slipstream
Here is a (translated) copy of an e-mail I have sent to another engineer...
The CPU has the bus when CLK is HIGH and the TED has the bus when CLK is LOW. The problem arises at the end of the CPU access to the DRAM so CLK = 1 and CAS = 0.
1. Access to RAM is confirmed only when CAS = 0 because RAS = 0 means either the low addresses are on the bus or a row # to refresh for the DRAM refresh cycle. RAS = 0 becomes irrelevant for static RAM that is connected to the non-multiplexed address bus.
2. When the TED has the BUS it only makes READs so if CLK = 0 then it is absolutely necessary that R/!W = 1.
3. When the CPU has the BUS, it can do READ or WRITE but because of the way the DRAM is handled in this machine, during a WRITE, CAS and R/!W line stay LOW after CLK goes from 1 to 0. So, then, there is a condition that is normally impossible; CAS = 0 and CLK = 0 and R /!W = 0 This condition is equivalent to doing a WRITE when the TED has the bus.
4. At that instant, address lines A0-A7 start to change because refresh cycles arrive 200ns later. The DRAM is not affected because of its multiplexed bus that 'latches' the low address lines at the beginning of the DRAM access cycle. On the other hand the static RAM, especially if it is fast, will see this change of addresses and start writing the data it reads on the data bus to this new address which is a mixture (A0-7) of the row to be refreshed at the next RAS = 0 and the still valid addresses present on A8 to A15.
So, the truth table for the !CS of the static RAM according to the CAS, CLK and R/!W entries should be as follows:
Code: Select all
CAS | CLK |R/!W | !CS
1 | X | X | 1 <- CAS is high so no access no matter the values of CLK and R/!W
0 | 1 | 1 | 0 <- CAS confirms CPU READ RAM access
0 | 1 | 0 | 0 <- CAS confirms CPU WRITE RAM access - It is in the few ns following this condition that there is a bug
0 | 0 | 1 | 0 <- CAS confirms TED READ RAM access
0 | 0 | 0 | 1 <- CAS confirms TED WRITE RAM access which is impossible - this 'anomaly' lasts 90ns after every CPU writes.
It's truly as if the people who designed this machine purposely made it very complicated to add memory. Adding DRAM can almost only be done by making mods on the board even when using a cartridge. Using SRAM requires needlessly complicated timing tricks.
What you see above is CAS going low to confirm an access to RAM by the CPU but it is still low when CLK goes low to signal it's time for the TED to have control of the bus. Worst, R/!W stays low too even longer when the TED can NEVER write to memory. A genuinely stupid way of working.
That was the least expensive and fastest way to design these machines at the time. Today DRAM is almost impossible to find and static RAM costs peanuts. This specific delay on the R/W line therefore becomes an issue that can be dealt with the addition of a simple single gate logic chip.
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